Peripheral init broken at any optimization above zero.

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Otatiaro
Posts: 41
Joined: Thu Nov 10, 2016 8:58 am

Peripheral init broken at any optimization above zero.

Postby Otatiaro » Thu Dec 22, 2016 8:52 pm

Hello,

I have a weird issue with optimization. I'm writing drivers, so far one for an USART, and one for an SPI.
Final app will require high performance, so I'm regularly checking that everything works fine on O3.
Target MCU is STM32F401CC, I do not use the hal nor the standard peripheral library, only the registers definition and their flags. The code is c++ only.


The USART driver went fine, I can init, receive and transmit (using DMAs) without any problem on O0, O3, Os, etc.

But the SPI driver triggers an IBUSERR as soon as optimization is set above O0 (even on Og !). I did check the compiled code and the disassembly seems fine, loading registers with values and modifying them with BIC.w and stuff. If I reorder some lines of code, then the hard fault error triggers on a different line (but always in the SPI init function, or just after returning from it). Isn't IBUSERR precise ? It seems there can be a few instructions before it triggers.

I'll post the code tomorrow, but does anybody already faced this kind of issue ?
I already did check the classical errors like uninitialized variables, etc.

Thomas.

Mattias Norlander
Posts: 172
Joined: Fri Apr 29, 2016 10:01 am

Re: Peripheral init broken at any optimization above zero.

Postby Mattias Norlander » Wed Jan 11, 2017 4:38 pm

Could you post the code?

Otatiaro
Posts: 41
Joined: Thu Nov 10, 2016 8:58 am

Re: Peripheral init broken at any optimization above zero.

Postby Otatiaro » Tue Feb 21, 2017 6:43 pm

Hello,

I forgot to update, but I did make it work, altough I don't know exactly why it was not working.

I was manually triggering the STM32 timer overflow so that the auto reload counter was updated (they are shadow registers), and this caused the problem, it seems if you enable an interrupt and trigger it in the next very few cycles, it does not correctly starts the ISR.

I delayed this trigger in a later stage of the init procedure and everything is working fine even on -O3.

Thomas.


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